EFFECTIVE INTRINSIC GETITERING FOR 200 mm AND 300 mm P/P- WAFERS IN LOW THERMAL BUDGET 0.13 μm ADVANCED CMOS LOGIC PROCESS

EFFECTIVE INTRINSIC GETITERING FOR 200 mm AND 300 mm P/P- WAFERS IN LOW THERMAL BUDGET 0.13 μm ADVANCED CMOS LOGIC PROCESS

Author(s):

Publication title:

Semiconductor silicon 2002 : proceedings of the ninth International Symposium on Silicon Materials Science and Technology

Title of ser.:

Electrochemical Society Proceedings Series

Ser. no.:

2002-2

Pub. Year:

2002

Page(from):

647

Page(to):

657

Pages:

11

Pub. info.:

Pennington, NJ: Electrochemical Society

ISSN:

01616374

ISBN:

9781566773744 [1566773741]

Language:

English

Call no.:

E23400/2002-2

Type:

Conference Proceedings

Details

TDL ID:	ZA00014035
Series ID:	PA00000028
Conf. info. (Name):	International Symposium on Silicon Materials Science and Technology
Conf. info. (Number):	9th
Conf. info. (Venue):	Philadelphia, PA, USA
Conf. info. (Date):	2002.05.13-2002.05.17

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