Gate Dielectric Thickness Control for High-K and Conventional Gate Stacks in the Presence of Chemical Oxides from Pre-gate Clean Processes for Sub-180 nm MOSFET Applications

Gate Dielectric Thickness Control for High-K and Conventional Gate Stacks in the Presence of Chemical Oxides from Pre-gate Clean Processes for Sub-180 nm MOSFET Applications

Author(s):

Guan, Jay J.

Publication title:

Semiconductor technology (ISTC 2001) : proceedings of the 1st International Conference on Semiconductor Technology

Title of ser.:

Electrochemical Society Proceedings Series

Ser. no.:

2001-17

Pub. Year:

2001

Page(from):

336

Page(to):

345

Pages:

10

Pub. info.:

Pennington, N.J.: Electrochemical Society

ISSN:

01616374

ISBN:

9781566773508 [1566773504]

Language:

English

Call no.:

E23400/200117

Type:

Conference Proceedings

Details

TDL ID:	ZA00014020
Series ID:	PA00000028
Conf. info. (Name):	International Conference on Semiconductor Technology - ISTC
Conf. info. (Number):	1st (2001)
Conf. info. (Venue):	Shanghai, China
Conf. info. (Date):	2001.05.27-2001.05.30

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