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Design rule optimization for 65-nm-node (CMOS5) BEOL using process and layout decomposition methodology

Author(s):
Honda, K. ( Toshiba Corp. (Japan) )
Peter, K. ( PDF Solutions Inc. (USA) )
Zhang, Y. ( PDF Solutions Inc. (USA) )
Yu, B. ( PDF Solutions Inc. (USA) )
Park, K. ( PDF Solutions Inc. (USA) )
Li, X. ( PDF Solutions Inc. (USA) )
Michaels, K. ( PDF Solutions Inc. (USA) )
Yamada, S. ( Toshiba Corp. (Japan) )
Noguchi, T. ( Toshiba Corp. (Japan) )
4 more
Publication title:
Design and process integration for microelectronic manufacturing II [sic] : 26-27 February 2004, Santa Clara, California, USA
Title of ser.:
Proceedings of SPIE - the International Society for Optical Engineering
Ser. no.:
5379
Pub. Year:
2004
Page(from):
111
Page(to):
118
Pages:
8
Pub. info.:
Bellingham, Wash., USA: SPIE - The International Society of Optical Engineering
ISSN:
0277786X
ISBN:
9780819452924 [0819452920]
Language:
English
Call no.:
P63600/5379
Type:
Conference Proceedings

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