Gate-leakage-tolerant circuits in deep sub-100-nm CMOS technologies

Gate-leakage-tolerant circuits in deep sub-100-nm CMOS technologies

Author(s):

Kang, S.-M. ( Univ. of California/Santa Cruz (USA) )
Yang, G. ( Univ. of California/Santa Cruz (USA) )
Wang, Z. ( Univ. of California/Santa Cruz (USA) )

Publication title:

Microelectronics: Design, Technology, and Packaging

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

5274

Pub. Year:

2004

Page(from):

56

Page(to):

66

Pages:

11

Pub. info.:

Bellingham, Wash.: SPIE - The International Society of Optical Engineering

ISSN:

0277786X

ISBN:

9780819451675 [0819451673]

Language:

English

Call no.:

P63600/5274

Type:

Conference Proceedings

Details

TDL ID:	ZA00013616
Series ID:	PA00000029
Conf. info. (Name):	Smart Materials, Nano-, and Micro- Smart Systems : Microelectronics
Conf. info. (Number):	2003
Conf. info. (Venue):	Perth, Australia
Conf. info. (Date):	2003.12.10-2003.12.12

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