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Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETs

Author(s):
Pack, R.C. ( Cadence Berkeley Labs. (USA) )
Axelrad, V. ( Sequoia Design Systems, Inc. (USA) )
Shibkov, A. ( Sequoia Design Systems, Inc. (USA) )
Boksha, V.V. ( Sequoia Design Systems, Inc. (USA) )
Huckabay, J.A. ( Cadence Design Systems, Inc. (USA) )
Salik, R. ( Cadence Design Systems, Inc. (USA) )
Staud, W. ( Cadence Design Systems, Inc. (USA) )
Wang, R. ( Motorola, Inc. (USA) )
Grobman, W.D. ( Motorola, Inc. (USA) )
4 more
Publication title:
Design and process integration for microelectronic manufacturing II : 26-28 February 2003, Santa Clara, California, USA
Title of ser.:
Proceedings of SPIE - the International Society for Optical Engineering
Ser. no.:
5042
Pub. Year:
2003
Page(from):
51
Page(to):
62
Pages:
12
Pub. info.:
Bellingham, Wash.: SPIE-The International Society for Optical Engineering
ISSN:
0277786X
ISBN:
9780819448477 [0819448478]
Language:
English
Call no.:
P63600/5042
Type:
Conference Proceedings

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