Chip Scale Polymer Stud Grid Array Packaging and Reliability Based on Low Cost Flip Chip Processing
- Author(s):
- Publication title:
- 2000 International Conference on High-Density Interconnect and Systems Packaging, 25-28 April 2000, The Adam's Mark Hotel, Denver, Colorado, USA
- Title of ser.:
- Proceedings of SPIE - the International Society for Optical Engineering
- Ser. no.:
- 4217
- Pub. Year:
- 2000
- Page(from):
- 118
- Page(to):
- 122
- Pages:
- 5
- Pub. info.:
- Reston, VA — Bellingham, Wash.: IMAPS — SPIE-The International Society for Optical
- ISSN:
- 0277786X
- ISBN:
- 9780930815608 [0930815602]
- Language:
- English
- Call no.:
- P63600/4217
- Type:
- Conference Proceedings
Similar Items:
1
Conference Proceedings
WAFER SCALE PACKAGING BASED ON UNDERFILL APPLIED AT WAFER LEVEL FOR LOW COST FLIP CHIP PROCESSING
IMAPS |
IMAPS |
IMAPS |
IMAPS |
3
Conference Proceedings
Initial Development Work on a High Throughput Low Cost Flip Chip on Board Assembly Process
IMAPS |
SPIE-The International Society for Optical Engineering |
Electrochemical Society |
SPIE - The International Society for Optical Engineering |
SPIE-The International Society for Optical Engineering |
IMAPS |
6
Conference Proceedings
Preliminary In-Process Stress Analysis of Flip-Chip Assemblies During Underfill
IMAPS |
SPIE-The International Society for Optical Engineering |