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Analysis of resist pattern collapse and optimization of DUV process for patterning sub-0.20-ｦﾌm gate line

Author(s):
Yu,J.Y. ( LG Semicon Co.,Ltd. (Korea) )
Jeong,G.-M. ( LG Semicon Co.,Ltd. (Korea) )
Huh,H. ( LG Semicon Co.,Ltd. (Korea) )
Kim,J.J. ( LG Semicon Co.,Ltd. (Korea) )
Kim,S.-P. ( LG Semicon Co.,Ltd. (Korea) )
Jeong,J.-K. ( LG Semicon Co.,Ltd. (Korea) )
Kim,H.-S. ( LG Semicon Co.,Ltd. (Korea) )
2 more
Publication title:
Advances in resist technology and processing XV : 23-25 February 1998, Santa Clara, California
Title of ser.:
Proceedings of SPIE - the International Society for Optical Engineering
Ser. no.:
3333
Pub. Year:
1998
Vol.:
Part 2
Page(from):
880
Page(to):
889
Pub. info.:
Bellingham, Wash., USA: SPIE-The International Society for Optical Engineering
ISSN:
0277786X
ISBN:
9780819427786 [0819427780]
Language:
English
Call no.:
P63600/3333
Type:
Conference Proceedings

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