Optimizing the clean effect of wafer backside in lithography developer process

Optimizing the clean effect of wafer backside in lithography developer process

Author(s):

Lin,H.-P. ( Taiwan Semiconductor Manufacturing Co. )
Chang,C.-H.
Lee,C.-H.
Pang,S.L.
Lu,K.L.

Publication title:

Process, equipment, and materials control in integrated circuit manufacturing V : 22-23 September, 1999, Santa Clara, California

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

3882

Pub. Year:

1999

Page(from):

193

Page(to):

199

Pub. info.:

Bellingham, Wash.: SPIE - The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819434791 [0819434795]

Language:

English

Call no.:

P63600/3882

Type:

Conference Proceedings

Details

TDL ID:	ZA00017165
Series ID:	PA00000029
Conf. info. (Name):	Microelectronic Manufacturing : Process, Equipment, and Materials Control in Intregrated Circuit Manufacturing
Conf. info. (Number):	1999 : 5th
Conf. info. (Venue):	Santa Clara, CA, USA
Conf. info. (Date):	1999.09.22-1999.09.23

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