Optimized shallow trench isolation for sub-0.18-ｦﾌm ASIC technologies

Optimized shallow trench isolation for sub-0.18-ｦﾌm ASIC technologies

Author(s):

Nouri,F. ( VLSI Technology,Inc. )

Laparra,O. ( VLSI Technology,Inc. )

Sur,H. ( VLSI Technology,Inc. )

Saha,S. ( VLSI Technology,Inc. )

Pramanik,D. ( VLSI Technology,Inc. )

Manley,M. ( VLSI Technology,Inc. )

1 more

Publication title:

Microelectronic device technology II : 23-24 September, 1998, Santa Clara, California

Title of ser.:

Proceedings of SPIE - the International Society for Optical Engineering

Ser. no.:

3506

Pub. Year:

1998

Page(from):

156

Page(to):

166

Pub. info.:

Bellingham, Washington: SPIE-The International Society for Optical Engineering

ISSN:

0277786X

ISBN:

9780819429650 [0819429651]

Language:

English

Call no.:

P63600/3506

Type:

Conference Proceedings

Details

TDL ID:	ZA00016438
Series ID:	PA00000029
Conf. info. (Name):	Microelectronic Manufacturing : Microelectronic device technology
Conf. info. (Number):	1998 : 2nd
Conf. info. (Venue):	Santa Clara, CA, USA
Conf. info. (Date):	1998.09.23-1998.09.24

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